The present invention relates to data processing, and more specifically, to methods, apparatus, and products for data streaming scheduling for dual chipset architectures that includes a high performance chipset and a low performance chipset.
Dual chipset architectures, sometimes referred to as big.LITTLE architectures, have both a high performance chipset and a low performance chipset. These architectures provide both high performance combined with extreme power efficiency to minimize energy consumption. The architecture comprehends the use of a powerful processor for the high peak use with a minimalist processor for times having low levels of data processing.
For example, modern computing systems utilize communications adapters, in the form of an expansion card or an on-board adapter, to communicate with other computers via a data communications network. Such communications adapters may be capable of sending and receiving data at extremely high rates. Such communications adapters can also consume significant amounts of power to support high data exchange rates, even when the communications adapters are sending and receiving data at rates that are well below their capabilities.